Technical Field
The embodiments described herein relate to the field of power management in computing systems, and more particularly system clock gating techniques.
Description of the Related Art
Computing systems typically include a number of interconnected integrated circuits or devices. In some cases, the integrated circuits may communicate through parallel interfaces, which simultaneously communicate multiple bits of data. In other cases, the integrated circuits may employ a serial interface, which sequentially communicates one bit of data at a time. For both parallel and serial interfaces, communicated data may be differentially encoded.
In some cases, the integrated circuits or devices within a computing system may communicate over the serial or parallel interfaces using one of various communication protocols. Such protocols may allow for the transmission of messages between various components of the computing system in addition to the transmission of data. The transmitted messages may include reports of levels of activity, requests for specific modes of operation, and the like.
During operation of a computing system, some components of the computing system may experience periods of time of limited or no use. Such periods of limited use may be used to conserve or reduce power by disabling portions of circuitry associated with an idle component. For example, circuits relating to the transmission of data on a communication bus (commonly referred to as “interface circuits,” “physical layer circuits,” or “PHYs”) may be disabled to reduce the power consumed the computing system.